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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-28310-2E
ASSP
1 CHANNEL 10-BIT D/A CONVERTER
MB40730
MB40730 is a low-power consumption, high-speed 10-bit D/A converter. The MB40730 is characterized by ECL (10 kH) compatible digital inputs, an analog output voltage from -2 to 0 V, and a maximum conversion rate of 60 MHz. It provides a reference voltage from a potential divider and band-gap reference, and can also use an external reference voltage. The MB40730 D/A converter is suitable for high-resolution TVs or VTRs.
20-PIN PLASTIC DIP
* Resolution: 10 bits * Conversion characteristics:
-Maximum conversion rate: 60 MHz (Minimum) -Linearity error: 0.1 % (Maximum) -Differential linearity error: 0.1 % (Maximum)
* Input and output:
-Digital input voltage: ECL (10 kH) levels -Analog output voltage: 2 Vp-p (-2 V to 0 V)
* Reference voltage:
-VROUT1: Potential divider circuit (VEEA 2/5.2) -VROUT2: Band-gap reference circuit (-2 V)
(DIP-20P-M01) 20-PIN PLASTIC SOP
*
-
Others: Supply voltage: -5.2 V single power supply Power dissipation: 180 mW (Typical value at analog output voltage 2 Vp-p) 140 mW (Typical value at analog output voltage 1 Vp-p)
ABSOLUTE MAXIMUM RATINGS (See NOTE)
(VCCA=VCCD=0 V, Ta=+25C) Parameter Analog power supply voltage Digital power supply voltage Power supply voltage difference Digital signal input voltage Storage Temperature NOTE: Symbol VEEA VEED VEED-VEEA VID Tstg Value -7.0 to 0 -7.0 to 0 1.0 0 to VEE -55 to +125 Unit V V V V C
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
(FPT-20P-M01)
Permanent device damage may occur if the above Absolute Maximum Rating are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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PIN ASSIGNMENT
(TOP VIEW) (MSB) D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 1 2 3 4 5 6 7 8 9 10 (DIP-20P-M01) (FPT-20P-M01) 20 19 18 17 16 15 14 13 12 11 CLK VCCD VCCA A.OUT VROUT2 VRIN VROUT1 COMP VEEA VEED
(LSB)
s
PIN DESCRIPTIONS
Pin No. 1 to 10 20 19 18 11 12 Symbol D1 to D10 CLK VCCD VCCA VEED VEEA I/O I I Description Data signal input pin (D1: MSB, D10: LSB) Clock signal input pin Digital ground pin (0 V) Analog ground pin (0 V) Digital power pin (-5.2 V) Analog ground pin (-5.2 V) Reference voltage input pin Analog output dynamic range setup pin Connect to pin 14 or 16 to use the built-in reference voltage When using an external reference voltage, the voltage on this pin must be from -2.20 V to -0.70 V Reference voltage output pin 1 The output voltage of the potential divider reference is fixed at VEEA 2/5.2. When this pin is connected to pin 15, the analog output voltage ranges from VEEA 2/5.2 to 0 V Reference voltage output pin 2 The output voltage of the band-gap reference is fixed at -2.0 V. When the pin is connected to pin 15, the analog output voltage ranges from -2 V to 0 V Phase compensation capacitor pin Insert a capacitor of 0.1 F or greater between VEEA and COMP for phase compensation Analog signal output pin
15
VRIN
I
14
VROUT1
O
16
VROUT2
O
13 17
COMP A. OUT
O
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BLOCK DIAGRAM
CLK A.OUT (MSB) D1 R D2 R 2R D3 R 2R D4 D5 D6 D7 R 2R D8 RR D9 D10 (LSB) VCCA Input Buffer 10 Masterslave Flip Flop 10 Buffer 10 Current Switch R 2R R 2R R 2R
VCCD Reference Resistor Amplifier
Reference Voltage 1 (potential divider reference) Reference Voltage 2 (band-gap reference)
VCCA
VEED VEEA
VROUT1
VROUT2
VRIN
COMP
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DIGITAL INPUT EQUIVALENT CIRCUIT
VCCD
D1 to D10 CLK
Threshold voltage = -1.3 V
VEED
s
ANALOG OUTPUT EQUIVALENT CIRCUIT
VCCA RO = 240 A.OUT IO VEEA
s
REFERENCE VOLTAGE OUTPUT EQUIVALENT CIRCUIT
VCCA 4 k VROUT1 6 k
VCCA
BGR
VEEA
+ VROUT2 RS *
*: Overcurrent-prevention resistor (2 k) for a short to GND.
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TYPICAL CONNECTION EXAMPLE
VCCD DATA Input D1 to D10
VCCA A. OUT VROUT2 VRIN VROUT1 COMP Connect to VROUT1, VROUT2 or external reference voltage.
CLK Input
CLK VEED VEEA 0.1 m
0.01 -5.2 V
47
2.2
2.2
47
0.01
s
RECOMMENDED OPERATING CONDITIONS
(VCCA=VCCD=0 V, Ta=-20C to +75C) Standard value Parameter Analog power supply voltage Digital power supply voltage Power supply voltage difference Symbol Min. Power supply voltage VEEA VEED VEEA-VEED VRIN -20C Digital input high voltage VIHD 25C 75C -20C Digital input low voltage VILD 25C 75C Clock frequency Setup time Hold time Clock minimum pulse width high Clock minimum pulse width low Phase compensation capacitor Operating temperature fCLK tsu th twH twL CCOMP Top -5.46 -5.46 -0.2 -2.20 -1.13 -1.95 -1.95 -1.95 8 2 6.5 6.5 0.1 -20 Typ. -5.20 -5.20 -2.00 Max. -4.94 -4.94 0.2 -0.70 -0.88 -0.81 -0.735 -1.48 60 75 V V V V V V V V V V MHz ns ns ns ns F C Unit
Analog reference voltage
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DC CHARACTERISTICS
(VEEA=VEED=-5.46 to -4.94 V, Ta=-20C to +75C) Parameter Symbol LE DLE IIHD IILD IRIN VROUT1 VROUT2 VOFS VOZS RO IEE Condition DC accuracy VRIN=-2.000V VEEA = -5.20 V VEED = -5.20 V VEEA = -5.20 V VEED = -5.20 V VRIN = -2.000 V Ta=+25C VEEA = -5.46 V VEED = -5.46 V VRIN = VROUT Standard values Min. -0.1 -2.100 -2.100 -20 -2.068 192 -59 Typ. -2.000 -2.000 100 0 -1.998 240 -34* Max. 10 0.1 0.1 5 10 -1.900 -1.900 -1.928 288 Unit bit % % A A A V V ppm/C mV V mA
Resolution Linearity error Differential linearity error Digital input current high Digital input current low Reference input current Potential divider reference Band-gap reference Reference voltage Reference voltage Temperature coefficient
Full-scale output voltage Zero-scale output voltage Output resistance Power dissipation * : VEEA = VEED = -5.20 V
s
AC CHARACTERISTICS
(VEEA= VEED=-5.46 to -4.94 V, Ta=-20C to +75C) Standard values Parameter Maximum conversion rate Output propagation delay time Output rise time Output fall time Settling time Symbol FS tpd tr tf tset CL = 15 pF A.OUT pin terminating resistance = 240 Conditions Min. 60 Typ. 7 5 5 -17.5 Max. MSPS ns ns ns ns Unit
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TIMING CHART
VIHD Data input VILD
tsu
th -1.3 V
-0.9 V
-1.7 V twH twL -0.9 V -1.3 V
VIHD Clock input VILD
-1.7 V
+1/2LSB VOFS 90% 50% Analog output 10% VOZS tr tsetLH tPLH tPHL tf tsetHL 90% 50% 10% +1/2LSB
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DAC OUTPUT VOLTAGE CHARACTERISTICS
Input D1 to D10 (VCCA) VOFS
Output A.OUT 0.000 V 0.000 V
1023
0
VOZS (VRIN)
-1.998 V -2.000 V 1 LSB = 2 mV
s
DAC OUTPUT VOLTAGE FORMULA IN IDEAL CONDITIONS
A.OUT = VCCA 1023 - N (VCCA - VRIN) 1024 (N : Digital input code from 0 to 1023)
VOFS = VCCA VOZS = VCCA 1023 1024 (VCCA - VRIN)
NOTES
1. Preventing Switching Noise To prevent switching noise in the analog output signal, connect noise limiting capacitors to the VEEA and VEED pins as close to the VCCA and VCCD pins as possible. Power Pattern To reduce parasitic impedance, the PC board pattern to the VCCA, VCCD, VEEA and VEED pins should be as wide as possible.
2.
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TYPICAL CHARACTERISTICS CURVES
1. Power Supply Current v.s. Ambient Temperature 2. Linearity Error v.s. Ambient Temperature
VEE = -5.46 V VRIN = VROUT1 0 -20 IEE, Power supply current (mA) -40 -60 -80 -100 -25 0 25 50 75 100 Ambient temperature Ta ( C)
LEM ,
VEE = -5.20 V VRIN = -2.000 V 0.1 0.08 0.06 0.04 0.02 0 -25 0 25 50 75 100 Ambient temperature Ta ( C)
Linearity error (%)
3. Differential Linearity Error v.s. Ambient Temperature VEE = -5.20 V VRIN = -2.000 V 0.1 0.08
DLEM , Differential linearity error (%)
4. Output Resistance v.s. Ambient Temperature
300 280 260 240 220 200 0 25 50 75 100 -25 0 25 50 75 100 Ambient temperature Ta ( C) Ambient temperature Ta ( C)
0.06 0.04 0.02 0 -25
RO, Output resistance ()
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5. Full-Scale Output Voltage v.s. Ambient Temperature VEE = -5.20 V VRIN = -2.000 V VCC (Reference) -10 VOFS, Full-scale output voltage (mV) -20 -30 -40 -50 -25 0 25 50 75 100 Ambient temperature Ta ( C)
6. Zero-Scale Output Voltage v.s. Ambient Temperature VEE = -5.20 V VRIN = -2.000 V -1.900
-1.950 VOZS, Zero-scale output voltage (V)
-2.000
-2.050
-2.100 -25 0 25 50 75 100 Ambient temperature Ta ( C)
7. VROUT1 Reference Output Voltage v.s. Ambient Temperature VEE = -5.20 V -1.900
8. VROUT2 Reference Output Voltage v.s. Ambient Temperature VEE = -5.20 V -1.900
-1.950 VROUT1, Reference -2.000 output voltage (V) -2.050 VROUT2, Reference output voltage (V)
-1.950
-2.000
-2.050
-2.100 -25 0 25 50 75 100 Ambient temperature Ta ( C)
-2.100 -25 0 25 50 75 100 Ambient temperature Ta ( C)
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9. VROUT2 Reference Output Voltage v.s. Power Supply Voltage Ta = 25C -1.900
10. Setup Time v.s. Ambient Temperature
VEE = -5.20 V 10 8 tsu, Setup time (ns) 6 4
Reference output voltage VROUT2 (V)
-1.950
-2.000
-2.050
2 0 -6.0 -5.5 -5.0 -4.5 -4.0 -25 0 25 50 75 100 Power supply voltage VCC (V) Ambient temperature Ta ( C)
-2.100 -6.5
11. Setup Time v.s. Power Supply Voltage
12. Hold Time v.s. Ambient Temperature
Ta = 25C 10 8 6 tsu, Setup time (ns) 4 2 0 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 Power supply voltage VEE (V) tn, Hold time (ns) 6 4 2 0 -2 -4
VEE = -5.20 V
-25
0
25
50
75
100
Ambient temperature Ta ( C)
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13. Hold Time v.s. Power Supply Voltage
14. Minimum Clock Pulse Width v.s. Ambient Temperature
Ta = 25 C 6 4 2 0 -2 -4 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 Power supply voltage VEE (V) 10 8 6 4 2 0
VEE = -5.20 V
tn, Hold time (ns)
twL/twH, Minimum clock pulse width (ns)
twL twH
-25
0
25
50
75
100
Ambient temperature Ta ( C)
15. Minimum Clock Pulse Width v.s. Power Supply Voltage
16. Rise Time / Fall Time v.s. Ambient Temperature VEE = -5.20 V VRIN = -2.000 V CL = 15 pF Analog output 240 termination (1 V amplitude) 10 8 6 4 twL 2 0
Ta = 25 C 10 8 6 4 2 0 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 Power supply voltage VEE (V)
twL/twH, Minimum clock pulse width (ns)
tr/tf, Rise time and fall time (ns)
twH
-25
0
25
50
75
100
Ambient temperature Ta ( C)
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17. Rise Time / Fall Time v.s. Power Supply Voltage Ta = 25 C VRIN = -2.000 V CL = 15 pF Analog output 240 termination (1 V amplitude) 10 8 tr/tf, Rise time and fall time (ns) 6 4 2 0 -6.5 -6.0 -5.5 -5.0 -4.5 -4.0 Power supply voltage VEE (V)
18. Quantization Noise v.s. Analog Output Frequency
70 60 50 S/Nq, Quantization noise (dB) 40 30 20 0 5 10 15 20 25 Analog output frequency fOUT (MHz)
fCLK = 15 MHz fCLK = 30 MHz fCLK = 60 MHz
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PACKAGE DIMENSIONS
20-LEAD PLASTIC DUAL IN-LINE PACKAGE (CASE No.: DIP-20P-M01)
+.008 +0.20 .970 -.012 (24.64 -0.30 )
15MAX
INDEX-1 .260.010 (6.600.25)
.300(7.62) TYP
INDEX-2 +.012 .034 -0 (0.86+0.30 ) -0 +.012 .050 -0 (1.27 +0.30 ) -0 .010.002 (0.250.05)
.172(4.36) MAX
.118(3.00) MIN .100(2.54) .050(1.27) MAX TYP .018.003 (0.460.08)
.020(0.51) MIN
(c)1991 FUJITSU LIMITED D20005S-3C
Dimensions in inches (millimeters)
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PACKAGE DIMENSIONS (Continued)
20-LEAD PLASTIC FLAT PACKAGE (CASE No.: FPT-20P-M01)
.089(2.25) MAX (MOUNTING HEIGHT) .002(0.05) MIN (STAND OFF HEIGHT) .307.016 (7.800.40) INDEX .209.012 (5.300.30) .020.008 (0.500.20) .050(1.27) TYP .018.004 (0.450.10) Details of "A" part "A" .008(0.20) .005(0.13) M +.002 +0.05 .006 (0.15 ) -.001 -0.02 +0.40 +.016 .268-.008 (6.80 -0.20 )
+0.25 +.010 .500-.008 (12.70 -0.20 )
.004(0.10) .450(11.43) REF
.020(0.50) .007(0.18) MAX .027(0.68) MAX
(c)1991 FUJITSU LIMITED F20003S-5C
Dimensions in inches (millimeters)
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MB40730
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 1015, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211, Japan Tel: (044) 754-3753 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED No. 51 Bras Basah Road, Plaza By The Park, #06-04 to #06-07 Singapore 189554 Tel: 336-1600 Fax: 336-1609
All Rights Reserved. Circuit diagrams utilizing Fujitsu products are included as a means of illustrating typical semiconductor applications. Complete information sufficient for construction purposes is not necessarily given. The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu assumes no responsibility for inaccuracies. The information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by Fujitsu. Fujitsu reserves the right to change products or specifications without notice. No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of Fujitsu. The information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear control systems or medical equipments for life support.
F9601 (c) FUJITSU LIMITED Printed in Japan

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